Introduction

The Lab

1. Using Digital Works, open the file "4bitDtest.dwm". This file is found on the network shared CST130 folder on the computer "Acme". Open Digital Works, then select "File" then "Open". Scroll down to "cst130 on 'Acme' (Y:)"" and click on it. Then open "4bitDtest.dwm".
2. Note that the 4 bit D Flip-Flop shown is positive-edge triggered and has, besides the clock and data inputs, a "R" (for Reset) input and a "LD" (for Load) input. Open the 4 bit D Flip-Flop macro and look carefully at the circuit.
1. When the load input is high (a logic 1), what signals are logically connected through the Muxes to the Flip-Flops D inputs?
2. When the load input is low (a logic 0), what signals are logically connected through the Muxes to the Flip-Flops D inputs?
3. So, when the load line is low, and the Flip-Flops are clocked, what will happen to the data stored in the Flip-Flops?
4. And, when the load line is high, and the Flip-Flops are clocked, what will happen to the data stored in the Flip-Flops?
3. Close the macro, and test your answers to the above questions on the circuit itself. First make sure the LD input is low, and the R input is low. Set up several different values on the D inputs, and pulse the clock input (take it high then low). Repeat the above with the LD input high and the R input low. Then fill in the blanks in the following statement: In order for Data to be loaded into this D Register, the R line must be low, the LD line must be _________ and the Clock line must have a _______ edge on it.

Because the LD (load) function cannot happen without an edge on the Clock, the LD input is said to be synchronous. Synchronous is a latin word which means with (syn) the clock (chronous).
4. Now, with some non-zero data loaded into the register and the clock line low, take the R line high.
• What happens?
• Does it matter whether the clock line is high or low when the R line is taken high?
• Does it matter whether the LD line is high or low?
• Can any data be loaded into the register when the R line is high?
Because the R (reset) function can happen independent of the clock it is said to be asynchronous. In latin, placing an "a" in front of a word makes the meaning oppose the meaning of the original word, So asynchronous means without the clock.
5. Now, open the file "regxfer.dwm" in the shared CST130 folder on Acme. Note that this circuit consists of 4 4-bit D registers, a 4-bit 4-to-1 mux, and a 4-bit adder/subtractor. Fill in the following table showing what is required on each of the inputs prior to the next positive-edge on the clock in order to make the required transfer of information. In some cases it doesn't matter what is on a particular input. In these cases place a slash in the cell. After you fill in each line, set up those inputs in the circuit and pulse the clock line in order to test the transfer.

 

	Switch Data Inputs		Sub/ Add		Load
Desired Transfer		Reset		S1 S0	Z	Y	X	W
Move a 1 from the switch inputs to the W register (only the W register)
Move a 7 from the switch inputs to the X register (only the X register)
Move X + W to the Z register (only the Z register)
Move X - W to the Y register (only the Y register)
Move the contents of the Z register to the X and W registers simultaneously (only X and W)
Move the contents of the Y register to the Z register (only the Z register)

6. Next, do whatever is necessary to get a 0000 into X, and a  0001 into W. Then set up the system so that register X gets X+W. Finally clock (pulse the clock line) the system repeatedly. What have we configured the system to do?                    Demonstrate this function to the instructor.
7. Now open the file "regtrixfer.dwm". This circuit performs the same function as the mux based register transfer circuit, but it uses tri-state buffers instead of a mux to determine the source of data placed on the system bus.
• Open the Y or Z registers and note the tri-state buffers that were added on the Q outputs. Also open the buffer block below the switch data inputs to see that this block contains nothing but tri-state buffers.
• Remember that in a tri-state buffer, when the enable line is not asserted, the output is effectively disconnected from the wire. It is as if a physical switch inside the buffer was opened up, disconnecting the output wire from the internal circuitry of the buffer. Thus the outputs of a tri-state buffer can be in one of three states -- High (1), Low (0) and disconnected, hence the name "tri-state".
• Also remember that no two tri-state devices should drive the data bus at the same time. At best, this leads to confusion since one device can be attempting to drive a line on the system bus high (1), while another device could be attempting to drive the same line low (0). At worst, in the world of real circuits, it can do electrical damage to the buffers. When two devices drive the same bus lines at the same time, it is called a "bus conflict". It can also be called "bus contention". Set up a situation in which there is bus contention on the system bus. Note that the Digital Works simulator detects this condition and resets the circuit.
8. Now, avoiding bus contention, do a number of register transfers using the tri-state based circuit.What one condition is required in this circuit in order to avoid bus contention?
9. Determine how a 2-to-4 decoder could be connected to the circuit in order to guarantee that bus contention can never occur.
   Note: a 2-to-4 decoder has 2 inputs -- I1 and I0 -- and 4 outputs -- O0, O1, O2 and O3. Only one of the outputs is ever 1 at any time. Output O0 is made a logic 1, only when I1,I0 = 00. Output O1 is made a logic 1 when I1, I0 = 01 and so on.
10. Create a macro containing a 2-to-4 decoder, and add it to the above tri-state based circuit with a switch labeled S0 connected to the I0 decoder input and a switch labeled S1 connected to the I1 decoder input. Connect the decoder outputs so that this circuit performs the same transfers as the mux based circuit (that is S1,S0 = 00 selects the switches as source, S1,S0 = 01 selects the adder outputs as source, S1,S0 = 10 selects register Y as source, and S1,S0 = 11 selects register Z as source).
11. Demonstrate your working circuit to the instructor.
12. Turn in answers to the questions in items 2, 3, 4, 5 (the flilled in table), 6 and 8. Also, turn in printouts of your 2-to-4 decoder macro, and the tri-state based register transfer circuit that you modified using the decoder.